1. Field of the Invention
Embodiments of the invention relate generally to the field of memory devices and more particularly, to a system and method of address mapping and section replacement within a memory device.
2. Description of the Related Art
DRAM memory is a volatile memory that can be electrically erased and reprogrammed. DRAM memory generally stores information via an access device (e.g., an FET) and a capacitor, which are generally referred to in combination as a “cell.” Each cell traditionally stores one bit of information that is represented as a “0” or a “1”. The memory device often includes a grid-like arrangement including rows and columns of cells that are referred to as a block. Multiple blocks are combined to form a memory array. Unfortunately, not all of the cells and blocks of the memory array are usable. For example, some cells and blocks are unusable (i.e., bad) when the memory device is manufactured and/or some of the cells and blocks fail over the life of the memory device. Memory device designers typically account for this with repair schemes that move the data from bad cells and blocks to good cells and blocks (e.g., redundant rows and/or columns within the memory array). Typically, these repair schemes employ techniques to redirect requests to the good cells (e.g., redundant rows).
Compared to older memory devices that included smaller storage capacities and smaller memory arrays, current memory devices include larger memory arrays with an increased number of cells and blocks. With the increase in the size and in the number of cells and blocks, there is an increase in the probability that a memory device will experience failures. Accordingly, one repair scheme may include increasing the number of redundant rows and columns to account for the increase in the number of expected failures. Unfortunately, as the redundancy within the memory increases, repair can become increasingly difficult for several reasons. For instance, the mere addition of redundant rows and columns can undesirably increase the size of the memory device. Further, addressing can become complex as the memory array becomes larger and the repair scheme covers the larger area of the memory array, and more devices may be employed to implement the repair scheme. Increases in complexity can also lead to decreases in the speed of the memory as more complex layouts and schemes are employed to access data.
Embodiments of the present invention may be directed to one or more of the problems set forth above.